PDLVDS-RX — photodiode LVDS receiver

Clean-room receiver for the Miniscope Zero optical uplink: Excelitas C30737LH Si APD → OPA657 TIA → LMH7220 comparator (LVDS out, DAC-set threshold) → ADN2813 CDR → STM32H723 + USB3300 USB-HS. Design target: 50 Mbps line rate, 8b/10b (40 Mbps payload); the paper's mode: 8 Mbps Manchester (16 Mbaud), as transmitted. LT3757 flyback APD bias 150–420 V. USB-C powered; verify on any laptop over USB, no FPGA attached.

Pass 186

2026-11-06 21:03 PST (2026-11-07T05:03:06Z UTC) · commit 77870ab (77870abfba793c240f851d00622bf801b4d9f991)

ADOPTED

Quadrant prep (zero audited delta): ULPI trio exits repacked to their designed positions - DIR via slid SW on its own B line to (75.5,17.521), CK via to its southern home (76.625,17.5), NXT F exit re-laid (74.65,17.8). All three nets stay connected; DRC 19 unconnected / 154 violations identical to exp215. STP dive gate now exactly characterised: DIR/CK vias 1.125 apart (track threads at 0.56/0.565, no via fits between - needs 1.4); the southern dive field is fenced by C20’s two pads, DM_PHY’s F vertical and C22.2 - completion needs the joint DM re-lay + C22/C20 shift packing

Nets fully routednot recorded
Pins failednot recorded
Clearance violations109
Unconnected nets16
Audit verdictFAIL

Routes — all copper layers and each layer

All layers
All layers — click the image to open the full-size SVG in a new tab.
All layersAll layers F.Cu layerF.CuIn1.Cu layerIn1.CuIn2.Cu layerIn2.CuB.Cu layerB.Cu

F.Cu In1.Cu In2.Cu B.Cu

Top

Pass 186 — top

Bottom

Pass 186 — bottom

← Pass 185 · all passes