PDLVDS-RX — photodiode LVDS receiver

Clean-room receiver for the Miniscope Zero optical uplink: Excelitas C30737LH Si APD → OPA657 TIA → LMH7220 comparator (LVDS out, DAC-set threshold) → ADN2813 CDR → STM32H723 + USB3300 USB-HS. Design target: 50 Mbps line rate, 8b/10b (40 Mbps payload); the paper's mode: 8 Mbps Manchester (16 Mbaud), as transmitted. LT3757 flyback APD bias 150–420 V. USB-C powered; verify on any laptop over USB, no FPGA attached.

Pass 9

2026-11-04 00:30 PST (2026-11-04T08:30:34Z UTC) · commit e8a0954 (e8a09549b812b52075500880970cce009af8e59f)

ADOPTED

Placement change, answering pass 8’s diagnosis: the U7/U12/L2/X1 cluster is moved on the pass-7 board to unbox pads that had no exit — 24 pad pairs removed, 0 added. Board saved as hw/pdlvds_rx.moved.kicad_pcb.

Nets fully routednot recorded
Pins failednot recorded
Clearance violations64
Unconnected nets69
Audit verdictFAIL

Routes — all copper layers and each layer

All layers
All layers — click the image to open the full-size SVG in a new tab.
All layersAll layers F.Cu layerF.CuIn1.Cu layerIn1.CuIn2.Cu layerIn2.CuB.Cu layerB.Cu

F.Cu In1.Cu In2.Cu B.Cu

Top

Pass 9 — top

Bottom

Pass 9 — bottom

Audit: results/audit-moved.txt, committed with the pass (copper items 1,392). No renders were committed for this pass. Renders backfilled on 2026-11-04 by rendering the board file as of this pass's commit; not contemporaneous with the pass. Composite render backfilled on 2026-11-04 by rendering the board file as of this pass's commit; not contemporaneous with the pass.

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