PDLVDS-RX — photodiode LVDS receiver

Clean-room receiver for the Miniscope Zero optical uplink: Excelitas C30737LH Si APD → OPA657 TIA → LMH7220 comparator (LVDS out, DAC-set threshold) → ADN2813 CDR → STM32H723 + USB3300 USB-HS. Design target: 50 Mbps line rate, 8b/10b (40 Mbps payload); the paper's mode: 8 Mbps Manchester (16 Mbaud), as transmitted. LT3757 flyback APD bias 150–420 V. USB-C powered; verify on any laptop over USB, no FPGA attached.

Pass 75

2026-11-04 18:40 PST (2026-11-05T02:40:54Z UTC) · commit 404dc5c (404dc5cfab4a29c61fc507f50959495d38d06333)

ADOPTED

GND stitches (exp10 -> exp12): the 8 non-main audit groups were all single F.Cu items inside the board-wide notch rect, cut off from the F/B pours — but the notch rule areas carve F/B only, so each was stitched by a via down to the continuous In1 GND plane. 7 pad stitches via hand_via (C32.2, C29.2, C30.2, U10.5, U10.11, T1.4, R28.2 — 7/7 placed) + 1 via on the lone GND track segment at (27.296,12.092) (hw/stitch_track.py, sampled along the segment under hand_via’s all-layer disc test). Group membership from hw/dump_groups.py (audit-exact union-find, full lists).

Nets fully routednot recorded
Pins failednot recorded
Clearance violations2
Unconnected nets32
Audit verdictFAIL

Routes — all copper layers and each layer

F.Cu In1.Cu In2.Cu B.Cu

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Pass 75 — top

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Pass 75 — bottom

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