PDLVDS-RX — photodiode LVDS receiver

Clean-room receiver for the Miniscope Zero optical uplink: Excelitas C30737LH Si APD → OPA657 TIA → LMH7220 comparator (LVDS out, DAC-set threshold) → ADN2813 CDR → STM32H723 + USB3300 USB-HS. Design target: 50 Mbps line rate, 8b/10b (40 Mbps payload); the paper's mode: 8 Mbps Manchester (16 Mbaud), as transmitted. LT3757 flyback APD bias 150–420 V. USB-C powered; verify on any laptop over USB, no FPGA attached.

Pass 4

2026-11-03 14:29 PST (2026-11-03T22:29:05Z UTC) · commit fb2acf7 (fb2acf7b80f74860a8301a3cce6eaf4df1abbb6f)

ADOPTED

Stricter clearance model in the router: vias never exempt, segment-midpoint tests, layer-aware HV clearance. Traded connections for correctness — 58 of 112 nets fully routed, 74 pins failed. First pass with a full audit committed: 98 unconnected nets, 341 clearance violations.

Nets fully routed58 of 112
Pins failed74
Clearance violations341
Unconnected nets98
Audit verdictFAIL

Routes — all copper layers and each layer

All layers
All layers — click the image to open the full-size SVG in a new tab.
All layersAll layers F.Cu layerF.CuIn1.Cu layerIn1.CuIn2.Cu layerIn2.CuB.Cu layerB.Cu

F.Cu In1.Cu In2.Cu B.Cu

Top

Pass 4 — top

Bottom

Pass 4 — bottom

Composite render backfilled on 2026-11-04 by rendering the board file as of this pass's commit; not contemporaneous with the pass.

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