PDLVDS-RX — photodiode LVDS receiver

Clean-room receiver for the Miniscope Zero optical uplink: Excelitas C30737LH Si APD → OPA657 TIA → LMH7220 comparator (LVDS out, DAC-set threshold) → ADN2813 CDR → STM32H723 + USB3300 USB-HS. Design target: 50 Mbps line rate, 8b/10b (40 Mbps payload); the paper's mode: 8 Mbps Manchester (16 Mbaud), as transmitted. LT3757 flyback APD bias 150–420 V. USB-C powered; verify on any laptop over USB, no FPGA attached.

Pass 170

2026-11-06 08:13 PST (2026-11-06T16:13:48Z UTC) · commit fcacae4 (fcacae4c2b7d8c0181727b1ce56d5787322d5d47)

ADOPTED

pass 170: DAC_VREF connected. Grid router proved F/B no-path; In2 segment (70.0,5.375)-(69.51,7.85) from the router, via (70.3,5.0) overlapping U8.10 pad edge joined by In2 stub, via (69.51,7.85) on-segment, F stub into C26.1. DRC: violations 156 (unchanged), unconnected 37 -> 36

Nets fully routednot recorded
Pins failednot recorded
Clearance violations96
Unconnected nets31
Audit verdictFAIL

Routes — all copper layers and each layer

All layers
All layers — click the image to open the full-size SVG in a new tab.
All layersAll layers F.Cu layerF.CuIn1.Cu layerIn1.CuIn2.Cu layerIn2.CuB.Cu layerB.Cu

F.Cu In1.Cu In2.Cu B.Cu

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