PDLVDS-RX — photodiode LVDS receiver

Clean-room receiver for the Miniscope Zero optical uplink: Excelitas C30737LH Si APD → OPA657 TIA → LMH7220 comparator (LVDS out, DAC-set threshold) → ADN2813 CDR → STM32H723 + USB3300 USB-HS. Design target: 50 Mbps line rate, 8b/10b (40 Mbps payload); the paper's mode: 8 Mbps Manchester (16 Mbaud), as transmitted. LT3757 flyback APD bias 150–420 V. USB-C powered; verify on any laptop over USB, no FPGA attached.

Pass 117

2026-11-05 13:35 PST (2026-11-05T21:35:24Z UTC) · commit 9a17ea0 (9a17ea002447bfff744c41df914933e09b2f317e)

ADOPTED

APD_K D1.5 leg connected (queue item 1, leg 2 of 3). D1.5 is ringed by its own footprint’s APD_A pads at 0.40-0.50 mm gaps, so any surface exit starts inside the 1.0 mm surface class – the geometry behind the 2 standing APD_K-vs-APD_A lines. Fix (hw/fix_d15.py): ONE diagonal F neck (9.20,40.00)->(11.00,38.50) whose exact-test blockers are D1.4 and D1.6 only (script asserts all blockers are APD_A and aborts otherwise), via at (11.00,38.50) (nearest clear site in a 0.25-grid disc scan), In1 south+east runs onto the main web’s via (13.62,30.62). DELTAS vs pass 116: nets 30->30 (APD_K groups 3->2; only the RJ2.2 leg remains), violations 72->74 (+2, exactly the two predicted sibling-pad lines APD_A (D1.4)/(D1.6) vs the neck track – same standing D1-footprint species as the 2 gated lines, geometrically forced: no via site reachable from D1.5 clears 1.0 mm from both pads). No victims.

Nets fully routednot recorded
Pins failednot recorded
Clearance violations74
Unconnected nets30
Audit verdictFAIL

Routes — all copper layers and each layer

F.Cu In1.Cu In2.Cu B.Cu

Top

Pass 117 — top

Bottom

Pass 117 — bottom

← Pass 116 · all passes · Pass 118 →