PDLVDS-RX — photodiode LVDS receiver

Clean-room receiver for the Miniscope Zero optical uplink: Excelitas C30737LH Si APD → OPA657 TIA → LMH7220 comparator (LVDS out, DAC-set threshold) → ADN2813 CDR → STM32H723 + USB3300 USB-HS. Design target: 50 Mbps line rate, 8b/10b (40 Mbps payload); the paper's mode: 8 Mbps Manchester (16 Mbaud), as transmitted. LT3757 flyback APD bias 150–420 V. USB-C powered; verify on any laptop over USB, no FPGA attached.

Pass 92

2026-11-05 03:56 PST (2026-11-05T11:56:56Z UTC) · commit 10642b3 (10642b30079d3153bd3d60af9a80a5d888d14aca)

ADOPTED

Escapes 9 (exp49 -> exp50): R50 moved (-2.0,-0.8) opening the HV_RAW via-gap lane, orphaned FBX/R31B hops ripped for re-route, U14.6 via down to B, VBUS picket ripped for CC2. Audit records the state.

Nets fully routednot recorded
Pins failednot recorded
Clearance violations82
Unconnected nets29
Audit verdictFAIL

Routes — all copper layers and each layer

All layers
All layers — click the image to open the full-size SVG in a new tab.
All layersAll layers F.Cu layerF.CuIn1.Cu layerIn1.CuIn2.Cu layerIn2.CuB.Cu layerB.Cu

F.Cu In1.Cu In2.Cu B.Cu

Top

Pass 92 — top

Bottom

Pass 92 — bottom

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