PDLVDS-RX — photodiode LVDS receiver

Clean-room receiver for the Miniscope Zero optical uplink: Excelitas C30737LH Si APD → OPA657 TIA → LMH7220 comparator (LVDS out, DAC-set threshold) → ADN2813 CDR → STM32H723 + USB3300 USB-HS. Design target: 50 Mbps line rate, 8b/10b (40 Mbps payload); the paper's mode: 8 Mbps Manchester (16 Mbaud), as transmitted. LT3757 flyback APD bias 150–420 V. USB-C powered; verify on any laptop over USB, no FPGA attached.

Pass 52

2026-11-04 12:07 PST (2026-11-04T20:07:19Z UTC) · commit 6bd1ae4 (6bd1ae40bb898fb8feefd20c5cfd4b013bfc4079)

ADOPTED

surgery2 with pad-aware blocker pricing (pads cost 10, tracks/vias 1): ULPI_NXT U7.11 stubbed south (3 ULPI_STP items ripped), THRADJ U4.9 stubbed (2 GND tracks ripped) — every formerly singleton pad on the board now has copper

Nets fully routednot recorded
Pins failednot recorded
Clearance violations3
Unconnected nets54
Audit verdictFAIL

Routes — all copper layers and each layer

F.Cu
F.Cu — click the image to open the full-size SVG in a new tab.
F.Cu layerF.CuIn1.Cu layerIn1.CuIn2.Cu layerIn2.CuB.Cu layerB.Cu

F.Cu In1.Cu In2.Cu B.Cu

Top

Pass 52 — top

Bottom

Pass 52 — bottom

← Pass 51 · all passes · Pass 53 →