PDLVDS-RX — photodiode LVDS receiver

Clean-room receiver for the Miniscope Zero optical uplink: Excelitas C30737LH Si APD → OPA657 TIA → LMH7220 comparator (LVDS out, DAC-set threshold) → ADN2813 CDR → STM32H723 + USB3300 USB-HS. Design target: 50 Mbps line rate, 8b/10b (40 Mbps payload); the paper's mode: 8 Mbps Manchester (16 Mbaud), as transmitted. LT3757 flyback APD bias 150–420 V. USB-C powered; verify on any laptop over USB, no FPGA attached.

Pass 171

2026-11-06 08:18 PST (2026-11-06T16:18:31Z UTC) · commit 9d9ad04 (9d9ad04c50ddf304b7ad5296ffabaf45628f2cfd)

ADOPTED

pass 171: APD_K + APD_A x2 connected. APD_K: In2 run (grid_route segment) (10.5,29.375)-(9.5,39.75) w0.4, via at C33.1 pad edge, via at D1.5 pad NE corner. APD_A: F jog from y38.375 web into D1.6, F bridge D1.3->D1.4 at y41.1 (both gaps were same-net 0.125/0.4 mm misses under the shield can). DRC: violations 156 (unchanged), unconnected 36 -> 33

Nets fully routednot recorded
Pins failednot recorded
Clearance violations101
Unconnected nets29
Audit verdictFAIL

Routes — all copper layers and each layer

All layers
All layers — click the image to open the full-size SVG in a new tab.
All layersAll layers F.Cu layerF.CuIn1.Cu layerIn1.CuIn2.Cu layerIn2.CuB.Cu layerB.Cu

F.Cu In1.Cu In2.Cu B.Cu

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Pass 171 — top

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