PDLVDS-RX — photodiode LVDS receiver

Clean-room receiver for the Miniscope Zero optical uplink: Excelitas C30737LH Si APD → OPA657 TIA → LMH7220 comparator (LVDS out, DAC-set threshold) → ADN2813 CDR → STM32H723 + USB3300 USB-HS. Design target: 50 Mbps line rate, 8b/10b (40 Mbps payload); the paper's mode: 8 Mbps Manchester (16 Mbaud), as transmitted. LT3757 flyback APD bias 150–420 V. USB-C powered; verify on any laptop over USB, no FPGA attached.

Pass 176

2026-11-06 11:36 PST (2026-11-06T19:36:34Z UTC) · commit ecfeede (ecfeedeee9ecdae7b6f104ede77acea97808cb24)

ADOPTED

pass 176: I2C_SDA U9.6 connected: via-in-pad d0.5/drill0.3 at (69.32,2.14) (centre shifted NE off pad centre: clears SCL via (69.375,1.375) d0.6 by 0.217 and U9.5 +3V3A pad by 0.21; on-centre placement measured 0.1904 vs SCL via), In2 single segment east (grid_route2) joining the SDA In2 chain at (71.125,1.875). KiCad DRC: unconnected 28 -> 27, violations 155 unchanged (clearance 0, shorting 0, dangling 0)

Nets fully routednot recorded
Pins failednot recorded
Clearance violations105
Unconnected nets24
Audit verdictFAIL

Routes — all copper layers and each layer

All layers
All layers — click the image to open the full-size SVG in a new tab.
All layersAll layers F.Cu layerF.CuIn1.Cu layerIn1.CuIn2.Cu layerIn2.CuB.Cu layerB.Cu

F.Cu In1.Cu In2.Cu B.Cu

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