PDLVDS-RX — photodiode LVDS receiver

Clean-room receiver for the Miniscope Zero optical uplink: Excelitas C30737LH Si APD → OPA657 TIA → LMH7220 comparator (LVDS out, DAC-set threshold) → ADN2813 CDR → STM32H723 + USB3300 USB-HS. Design target: 50 Mbps line rate, 8b/10b (40 Mbps payload); the paper's mode: 8 Mbps Manchester (16 Mbaud), as transmitted. LT3757 flyback APD bias 150–420 V. USB-C powered; verify on any laptop over USB, no FPGA attached.

Pass 177

2026-11-06 12:47 PST (2026-11-06T20:47:49Z UTC) · commit 200ac19 (200ac191c04aa391b51c3e4b6727776de00fd0cb)

ADOPTED

pass 177: ULPI district re-fanout — C48 moved east (+0.85,-0.15) with +3V3D feed re-routed between C19.1/C19.2 to via (81.625,10.9) on the B trunk; ULPI_D1 ripped and re-fanned on F (west channel x79.18/x79.05/x79.35 with jogs around D0’s staircase bulge); ULPI_D2 connected U7.22->U6.47 (F mouth, via (79.87,12.97) d0.5, In2 south, via (80.0,8.3), heal F staircase tail). DRC: unconnected 27->26, violations 155->156 (+1 silk_overlap from C48’s moved silkscreen, same existing class); clearance/shorting/dangling remain 0

Nets fully routednot recorded
Pins failednot recorded
Clearance violations108
Unconnected nets23
Audit verdictFAIL

Routes — all copper layers and each layer

F.Cu In1.Cu In2.Cu B.Cu

Top

Pass 177 — top

Bottom

Pass 177 — bottom

← Pass 176 · all passes · Pass 178 →