PDLVDS-RX — photodiode LVDS receiver

Clean-room receiver for the Miniscope Zero optical uplink: Excelitas C30737LH Si APD → OPA657 TIA → LMH7220 comparator (LVDS out, DAC-set threshold) → ADN2813 CDR → STM32H723 + USB3300 USB-HS. Design target: 50 Mbps line rate, 8b/10b (40 Mbps payload); the paper's mode: 8 Mbps Manchester (16 Mbaud), as transmitted. LT3757 flyback APD bias 150–420 V. USB-C powered; verify on any laptop over USB, no FPGA attached.

Pass 183

2026-11-06 18:55 PST (2026-11-07T02:55:23Z UTC) · commit c36125c (c36125c11d0d2540ddbd69a97c513be759af8e52)

ADOPTED

REFCLK In2 window re-lay: staircase (68.875,27.875)-(66.375,31.625) shifted east (+0.50 growing to +1.04), widening the DM_PHY/REFCLK channel from ~0.75 to 1.25-1.66 mm so the sealed ULPI trio pocket gains via crossings. REFCLK stays connected; KiCad DRC audited delta zero (154 violations / 21 unconnected, identical class table). District prep for the trio hauls, as pass 182 was for this one.

Nets fully routednot recorded
Pins failednot recorded
Clearance violations108
Unconnected nets18
Audit verdictFAIL

Routes — all copper layers and each layer

All layers
All layers — click the image to open the full-size SVG in a new tab.
All layersAll layers F.Cu layerF.CuIn1.Cu layerIn1.CuIn2.Cu layerIn2.CuB.Cu layerB.Cu

F.Cu In1.Cu In2.Cu B.Cu

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