PDLVDS-RX — photodiode LVDS receiver

Clean-room receiver for the Miniscope Zero optical uplink: Excelitas C30737LH Si APD → OPA657 TIA → LMH7220 comparator (LVDS out, DAC-set threshold) → ADN2813 CDR → STM32H723 + USB3300 USB-HS. Design target: 50 Mbps line rate, 8b/10b (40 Mbps payload); the paper's mode: 8 Mbps Manchester (16 Mbaud), as transmitted. LT3757 flyback APD bias 150–420 V. USB-C powered; verify on any laptop over USB, no FPGA attached.

Pass 185

2026-11-06 20:52 PST (2026-11-07T04:52:36Z UTC) · commit 7727f99 (7727f991af654003619c05ce5be2447dc4565aa2)

ADOPTED

ULPI_NXT connected: DM_PHY In2 vertical shifted 0.50 west opening the canyon gate; NXT re-routed through the gate and DIR’s old window via on the DRC-rule grid router, DIR re-planned around it; I2C_SDA mouth via moved and a GND track tie heals the U6.31 fill scrap. DRC unconnected 20->19, violations 154 identical, zero new

Nets fully routednot recorded
Pins failednot recorded
Clearance violations109
Unconnected nets16
Audit verdictFAIL

Routes — all copper layers and each layer

All layers
All layers — click the image to open the full-size SVG in a new tab.
All layersAll layers F.Cu layerF.CuIn1.Cu layerIn1.CuIn2.Cu layerIn2.CuB.Cu layerB.Cu

F.Cu In1.Cu In2.Cu B.Cu

Top

Pass 185 — top

Bottom

Pass 185 — bottom

← Pass 184 · all passes · Pass 186 →