PDLVDS-RX — photodiode LVDS receiver

Clean-room receiver for the Miniscope Zero optical uplink: Excelitas C30737LH Si APD → OPA657 TIA → LMH7220 comparator (LVDS out, DAC-set threshold) → ADN2813 CDR → STM32H723 + USB3300 USB-HS. Design target: 50 Mbps line rate, 8b/10b (40 Mbps payload); the paper's mode: 8 Mbps Manchester (16 Mbaud), as transmitted. LT3757 flyback APD bias 150–420 V. USB-C powered; verify on any laptop over USB, no FPGA attached.

Pass 91

2026-11-05 03:39 PST (2026-11-05T11:39:02Z UTC) · commit 6d96307 (6d963074a40af544cac00855c919bf1f501d93db)

ADOPTED

Escapes 3-8 (exp42 -> exp49): +3V3A COMPLETE (U7.6 west exit, In2 hop under the ULPI bank), HV_INTVCC COMPLETE (neck-width turn through the EP/GATE window, via-up hunted to (13.4,-10.8)), HV_SS stubbed to In2, HV_FBX stubbed to a via, R34 moved 1.5mm north (placement) with APD_K/TP_HV re-joins placed. Board state per audit.

Nets fully routednot recorded
Pins failednot recorded
Clearance violations80
Unconnected nets27
Audit verdictFAIL

Routes — all copper layers and each layer

All layers
All layers — click the image to open the full-size SVG in a new tab.
All layersAll layers F.Cu layerF.CuIn1.Cu layerIn1.CuIn2.Cu layerIn2.CuB.Cu layerB.Cu

F.Cu In1.Cu In2.Cu B.Cu

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