PDLVDS-RX — photodiode LVDS receiver

Clean-room receiver for the Miniscope Zero optical uplink: Excelitas C30737LH Si APD → OPA657 TIA → LMH7220 comparator (LVDS out, DAC-set threshold) → ADN2813 CDR → STM32H723 + USB3300 USB-HS. Design target: 50 Mbps line rate, 8b/10b (40 Mbps payload); the paper's mode: 8 Mbps Manchester (16 Mbaud), as transmitted. LT3757 flyback APD bias 150–420 V. USB-C powered; verify on any laptop over USB, no FPGA attached.

Pass 65

2026-11-04 14:10 PST (2026-11-04T22:10:13Z UTC) · commit 2e43811 (2e43811ed61a07825dc858263b14d76a2769db1f)

ADOPTED

EXPANSION: outline 100x80 -> 100x110 mm (+30 mm north — the only side moving neither connector edge (J1 south, J2 east) nor the APD/TIA cluster (D1/U1/R1 west)). 44 footprints moved as 4 rigid groups into the new strip (hw/expand_board.py; membership from signal-net BFS + decoupling radius, hw/groups_expand.py): U7 USB cluster 8 parts, U4 CDR cluster 14 (incl. U5 capture chain), U9 alone, U10 HV cluster 21 (incl. hand-verified secondary chain D5/C32/R29/R34). Copper of the 63 nets touching moved pads ripped (3215 tracks, 195 vias, 181 GND stubs at moved pads); every other net’s copper verified untouched (6110 -> 2519 items, exact difference). Courtyard overlap pairs 34 -> 18, pairs involving a moved part 16 -> 0 (6 intra-group grazes cleared by measured nudges); the 18 remaining pairs are all between unmoved parts (2 inside the frozen analog cluster, U6 field, MH5, J3) and cannot be zeroed without breaking the freeze. Cluster moats (min pad-centre distance to nearest foreign part): U7 1.54 -> 4.46 mm, U4 1.13 -> 3.99, U9 3.46 -> 5.09, U10 3.54 -> 3.99. U9’s four sealed pins: escape fans 12-13/16 -> 16/16. Unrouted placement state by design — the strip gets routed next.

Nets fully routednot recorded
Pins failednot recorded
Clearance violations2
Unconnected nets69
Audit verdictFAIL

Routes — all copper layers and each layer

F.Cu In1.Cu In2.Cu B.Cu

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