PDLVDS-RX — photodiode LVDS receiver

Clean-room receiver for the Miniscope Zero optical uplink: Excelitas C30737LH Si APD → OPA657 TIA → LMH7220 comparator (LVDS out, DAC-set threshold) → ADN2813 CDR → STM32H723 + USB3300 USB-HS. Design target: 50 Mbps line rate, 8b/10b (40 Mbps payload); the paper's mode: 8 Mbps Manchester (16 Mbaud), as transmitted. LT3757 flyback APD bias 150–420 V. USB-C powered; verify on any laptop over USB, no FPGA attached.

Pass 169

2026-11-06 08:10 PST (2026-11-06T16:10:13Z UTC) · commit bb21833 (bb218332abe2d847b14cd1286ad1d841464c764d)

ADOPTED

pass 169: SET_P + ILIM_A connected via +5V relays. SET_P: +5V F hook (41.8,51.25)-(42.375,50.125) relayed to In2 (vias 42.15,51.35 / 42.3,49.9), SET_P straight F run U13.7->R40.1 at y50.75. ILIM_A: +5V w0.6 staircase west of U14 relayed 0.35 west, U14.5 via (52.6,48.35) + In2 south run + via-in-pad R43.1 (55.5,50.8). DRC: violations 156 (unchanged classes), unconnected 39 -> 37

Nets fully routednot recorded
Pins failednot recorded
Clearance violations95
Unconnected nets32
Audit verdictFAIL

Routes — all copper layers and each layer

All layers
All layers — click the image to open the full-size SVG in a new tab.
All layersAll layers F.Cu layerF.CuIn1.Cu layerIn1.CuIn2.Cu layerIn2.CuB.Cu layerB.Cu

F.Cu In1.Cu In2.Cu B.Cu

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