PDLVDS-RX — photodiode LVDS receiver

Clean-room receiver for the Miniscope Zero optical uplink: Excelitas C30737LH Si APD → OPA657 TIA → LMH7220 comparator (LVDS out, DAC-set threshold) → ADN2813 CDR → STM32H723 + USB3300 USB-HS. Design target: 50 Mbps line rate, 8b/10b (40 Mbps payload); the paper's mode: 8 Mbps Manchester (16 Mbaud), as transmitted. LT3757 flyback APD bias 150–420 V. USB-C powered; verify on any laptop over USB, no FPGA attached.

Pass 82

2026-11-05 00:27 PST (2026-11-05T08:27:06Z UTC) · commit 929ba23 (929ba23638bd8ee3ac81615e8b2cf77484dc1a6a)

ADOPTED

SECURE (pass 82): commit the best on-disk board after the coordinator succession + VM replacement. Audited every exp board exp29-exp34 with the corrected checker: exp29 44/69, exp30 44/92, exp31 43/87, exp32 44/69, exp33 43/69, exp34 43/92. exp33 dominates: same 43 unconnected as exp34 with 23 fewer violations. Predecessor’s hops.py surgery (written against exp34) never saved – it crashed on the TP_HV re-stitch (blocked by HV_FBX at R50.2) before board.Save, so exp35 does not exist; the surgery script is committed separately and will be re-based onto exp33. bridge.py verified clean vs HEAD (no uncommitted changes). This pass changes no copper: it records exp33 as the secured base for the drain.

Nets fully routednot recorded
Pins failednot recorded
Clearance violations87
Unconnected nets43
Audit verdictFAIL

Routes — all copper layers and each layer

F.Cu In1.Cu In2.Cu B.Cu

Top

Pass 82 — top

Bottom

Pass 82 — bottom

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