PDLVDS-RX — photodiode LVDS receiver

Clean-room receiver for the Miniscope Zero optical uplink: Excelitas C30737LH Si APD → OPA657 TIA → LMH7220 comparator (LVDS out, DAC-set threshold) → ADN2813 CDR → STM32H723 + USB3300 USB-HS. Design target: 50 Mbps line rate, 8b/10b (40 Mbps payload); the paper's mode: 8 Mbps Manchester (16 Mbaud), as transmitted. LT3757 flyback APD bias 150–420 V. USB-C powered; verify on any laptop over USB, no FPGA attached.

Pass 174

2026-11-06 11:13 PST (2026-11-06T19:13:37Z UTC) · commit fbc3caa (fbc3caa1416a7008768462cd01e1c7520b9caa8e)

ADOPTED

pass 174: north-row group — C15 nudged +1.05mm N and C14 +1.0mm E (placement iteration); CF1 re-landed via north detour y43.1, CF2 extended into moved pad; REFCLKN connected (F channel y40.44, arc over +3V3D via, gap via (66.5,41.35), B east + dive to C14.1); +3V3D_CDR U4.12 connected (F stub, via (66.2,40.55), In2 drop to own staircase vertex (66.625,38.375)). KiCad DRC: unconnected 31->29, violations 156->155 (clearance 0, shorting 0, dangling 0)

Nets fully routednot recorded
Pins failednot recorded
Clearance violations104
Unconnected nets25
Audit verdictFAIL

Routes — all copper layers and each layer

All layers
All layers — click the image to open the full-size SVG in a new tab.
All layersAll layers F.Cu layerF.CuIn1.Cu layerIn1.CuIn2.Cu layerIn2.CuB.Cu layerB.Cu

F.Cu In1.Cu In2.Cu B.Cu

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