PDLVDS-RX — photodiode LVDS receiver

Clean-room receiver for the Miniscope Zero optical uplink: Excelitas C30737LH Si APD → OPA657 TIA → LMH7220 comparator (LVDS out, DAC-set threshold) → ADN2813 CDR → STM32H723 + USB3300 USB-HS. Design target: 50 Mbps line rate, 8b/10b (40 Mbps payload); the paper's mode: 8 Mbps Manchester (16 Mbaud), as transmitted. LT3757 flyback APD bias 150–420 V. USB-C powered; verify on any laptop over USB, no FPGA attached.

Pass 57

2026-11-04 12:14 PST (2026-11-04T20:14:26Z UTC) · commit 9f1ce83 (9f1ce83f645b53e190761b2166aeecbd036c0de1)

ADOPTED

hand bridges (hw/bridge.py): VBUS_RAW, ULPI_D0 and +5V group pairs bridged across 1.0-1.45 mm gaps, one fence item ripped each

Nets fully routednot recorded
Pins failednot recorded
Clearance violations3
Unconnected nets37
Audit verdictFAIL

Routes — all copper layers and each layer

F.Cu
F.Cu — click the image to open the full-size SVG in a new tab.
F.Cu layerF.CuIn1.Cu layerIn1.CuIn2.Cu layerIn2.CuB.Cu layerB.Cu

F.Cu In1.Cu In2.Cu B.Cu

Top

Pass 57 — top

Bottom

Pass 57 — bottom

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