PDLVDS-RX — photodiode LVDS receiver

Clean-room receiver for the Miniscope Zero optical uplink: Excelitas C30737LH Si APD → OPA657 TIA → LMH7220 comparator (LVDS out, DAC-set threshold) → ADN2813 CDR → STM32H723 + USB3300 USB-HS. Design target: 50 Mbps line rate, 8b/10b (40 Mbps payload); the paper's mode: 8 Mbps Manchester (16 Mbaud), as transmitted. LT3757 flyback APD bias 150–420 V. USB-C powered; verify on any laptop over USB, no FPGA attached.

Pass 1

2026-11-03 11:43 PST (2026-11-03T19:43:45Z UTC) · commit d0c0bca (d0c0bca09143177ae7a3f59f2cc6b8dc8500739a)

ADOPTED

Placement only: 144 footprints placed, GND zones and the HV isolation slot drawn, saved unrouted — the routing run was interrupted by a VM replacement. First committed board state; 0 of 112 nets routed.

Nets fully routed0 of 112
Pins failednot recorded
Clearance violationsnot recorded
Unconnected netsnot recorded
Audit verdictnot recorded

Routes — all copper layers and each layer

All layers
All layers — click the image to open the full-size SVG in a new tab.
All layersAll layers F.Cu layerF.CuIn1.Cu layerIn1.CuIn2.Cu layerIn2.CuB.Cu layerB.Cu

F.Cu In1.Cu In2.Cu B.Cu

Top

Pass 1 — top

Bottom

Pass 1 — bottom

Snapshot renders were made later from the board as committed at d0c0bca. Composite render backfilled on 2026-11-04 by rendering the board file as of this pass's commit; not contemporaneous with the pass.

all passes · Pass 2 →