PDLVDS-RX — photodiode LVDS receiver

Clean-room receiver for the Miniscope Zero optical uplink: Excelitas C30737LH Si APD → OPA657 TIA → LMH7220 comparator (LVDS out, DAC-set threshold) → ADN2813 CDR → STM32H723 + USB3300 USB-HS. Design target: 50 Mbps line rate, 8b/10b (40 Mbps payload); the paper's mode: 8 Mbps Manchester (16 Mbaud), as transmitted. LT3757 flyback APD bias 150–420 V. USB-C powered; verify on any laptop over USB, no FPGA attached.

Pass 114

2026-11-05 12:29 PST (2026-11-05T20:29:34Z UTC) · commit 2250037 (22500376c306fc100b4669497a6822c73f1cac1c)

ADOPTED

Drainable queue harvest (parent queue-order directive). LANDED: CAP_CLK fully connected (thread_far from the U6.34 west lane, gap 2.55); CC2 connected (bridge, gap 1.20); APD_K R31.1 joined the main group (bridge gap 2.72 then 0.02 after its first seg landed short); GND stitch clusters merged 5->4 groups (bridge gap 0.25). VICTIMS NAMED AND MOSTLY REPAID: CAP_CLK thread ripped BOOT0 (re-threaded, gap 7.75); CC2 bridge ripped VBUS_RAW (re-bridged, gap 0.85); APD_K bridge ripped HV_FBX x2 in the (31,-2.5) field – HV_FBX STILL SPLIT (bridge gap 1.33 unplaced; repay is next); BOOT0 thread ripped ULPI_STP’s U6.26 neck track (71.34,-2.25) – STP’s U6 group is a bare pad again, repay queued with the knot work (priced mechanisms still parked per directive). thread_far went 0/8 on VCAP2/PHY_1V8A/XI/+3V3A/PHY_1V8/USB_RST/XO/CF2 (anchor wall / pair gate) and heal_big 0/2 on CAP_CLK/CDR_LOL pad groups (fanout model: starts are pad cells only). CDR_LOL lane anchor in place at (69.9,2.75) for the east-column re-lay.

Nets fully routednot recorded
Pins failednot recorded
Clearance violations83
Unconnected nets31
Audit verdictFAIL

Routes — all copper layers and each layer

F.Cu In1.Cu In2.Cu B.Cu

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Pass 114 — top

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Pass 114 — bottom

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