PDLVDS-RX — photodiode LVDS receiver

Clean-room receiver for the Miniscope Zero optical uplink: Excelitas C30737LH Si APD → OPA657 TIA → LMH7220 comparator (LVDS out, DAC-set threshold) → ADN2813 CDR → STM32H723 + USB3300 USB-HS. Design target: 50 Mbps line rate, 8b/10b (40 Mbps payload); the paper's mode: 8 Mbps Manchester (16 Mbaud), as transmitted. LT3757 flyback APD bias 150–420 V. USB-C powered; verify on any laptop over USB, no FPGA attached.

Pass 88

2026-11-05 02:20 PST (2026-11-05T10:20:20Z UTC) · commit d7173aa (d7173aa4079fb6aefa3a50c0fbe9b3ef65491db9)

ADOPTED

Thread sweep 2 (exp39 -> exp40): CDR_NIN completed (9.80 thread, 2 rips), CMP_QN threaded (2.14), GND and HV_FBX one pair each, HV_RAW hairline (0.01). Audit: nets 32 -> 31, violations 75 (thread rips keep the violation count flat while nets drain; the violation campaign follows the drain). Remaining 31 nets by refusal species: anchor-walled (+3V3A, +3V3D_CDR, +5V, APD_K, CC2, PHY_1V8/A, SLICEN), lattice no-thread (HV_INTVCC, HV_SS, SET_P), pairs beyond the 15 mm gate (ULPI x8, USB_RST, CAP_DATA, CDR_PIN, CDR_SQUELCH, CF2, DP_PHY, FLY_PRI, HV_SHDN). Next: heal_big over the full residue (different start machinery than thread’s anchor), then hand escapes for what survives.

Nets fully routednot recorded
Pins failednot recorded
Clearance violations75
Unconnected nets31
Audit verdictFAIL

Routes — all copper layers and each layer

All layers
All layers — click the image to open the full-size SVG in a new tab.
All layersAll layers F.Cu layerF.CuIn1.Cu layerIn1.CuIn2.Cu layerIn2.CuB.Cu layerB.Cu

F.Cu In1.Cu In2.Cu B.Cu

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