PDLVDS-RX — photodiode LVDS receiver

Clean-room receiver for the Miniscope Zero optical uplink: Excelitas C30737LH Si APD → OPA657 TIA → LMH7220 comparator (LVDS out, DAC-set threshold) → ADN2813 CDR → STM32H723 + USB3300 USB-HS. Design target: 50 Mbps line rate, 8b/10b (40 Mbps payload); the paper's mode: 8 Mbps Manchester (16 Mbaud), as transmitted. LT3757 flyback APD bias 150–420 V. USB-C powered; verify on any laptop over USB, no FPGA attached.

Pass 179

2026-11-06 15:15 PST (2026-11-06T23:15:37Z UTC) · commit 7872e91 (7872e9179812cc7880bcf30d1ca440c0d2bf8721)

ADOPTED

pass 179: SLICEP + SLICEN connected (U4 west braid joint re-fanout) — C51 moved west to (58.75,39.25) with its +3V3D_CDR feed re-laid south of the staircase via; C13 moved to (59.0,41.75) (its pads carry only SLICEP/SLICEN); CDR_PIN jog re-laid west (post (62.875,37.875)->(62.55,37.8)) which unseals SLICEP’s diagonal (the jog post + U4.8 NW corner + 0.2 clearances provably sealed the wedge); SLICEP F diagonal + via (62.05,39.8) + In2 + tail into C13.1; SLICEN flat y38.575 + vertical dive x63.0 + via (63.0,39.35) + B west + tail into C13.2; GND stitch vias (63.85,39.15) and (59.0,38.9) re-tie the two F fill islands the new tracks severed. DRC: unconnected 25->23, violations 156->154 (silk 146->144), clearance/shorting/dangling 0; check_pcb courtyard 0, fallback 21 (SH1 only)

Nets fully routednot recorded
Pins failednot recorded
Clearance violations108
Unconnected nets20
Audit verdictFAIL

Routes — all copper layers and each layer

All layers
All layers — click the image to open the full-size SVG in a new tab.
All layersAll layers F.Cu layerF.CuIn1.Cu layerIn1.CuIn2.Cu layerIn2.CuB.Cu layerB.Cu

F.Cu In1.Cu In2.Cu B.Cu

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Pass 179 — top

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