PDLVDS-RX — photodiode LVDS receiver

Clean-room receiver for the Miniscope Zero optical uplink: Excelitas C30737LH Si APD → OPA657 TIA → LMH7220 comparator (LVDS out, DAC-set threshold) → ADN2813 CDR → STM32H723 + USB3300 USB-HS. Design target: 50 Mbps line rate, 8b/10b (40 Mbps payload); the paper's mode: 8 Mbps Manchester (16 Mbaud), as transmitted. LT3757 flyback APD bias 150–420 V. USB-C powered; verify on any laptop over USB, no FPGA attached.

Pass 106

2026-11-05 05:59 PST (2026-11-05T13:59:22Z UTC) · commit b87c4ee (b87c4eecd254424a252052898bc8011dba4094e1)

ADOPTED

Escapes 21 (exp67 -> exp68): D5 F stubs ripped for the D4/D5 order fix; D4 and D2 hand routes refused on named blockers (CDR_DATP via, U7.23 pad) – re-aimed in batches 22-24. exp66/exp67 were engine-attempt states with no connectivity change, folded here.

Nets fully routednot recorded
Pins failednot recorded
Clearance violations81
Unconnected nets59
Audit verdictFAIL

Routes — all copper layers and each layer

All layers
All layers — click the image to open the full-size SVG in a new tab.
All layersAll layers F.Cu layerF.CuIn1.Cu layerIn1.CuIn2.Cu layerIn2.CuB.Cu layerB.Cu

F.Cu In1.Cu In2.Cu B.Cu

Top

Pass 106 — top

Bottom

Pass 106 — bottom

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