PDLVDS-RX — photodiode LVDS receiver

Clean-room receiver for the Miniscope Zero optical uplink: Excelitas C30737LH Si APD → OPA657 TIA → LMH7220 comparator (LVDS out, DAC-set threshold) → ADN2813 CDR → STM32H723 + USB3300 USB-HS. Design target: 50 Mbps line rate, 8b/10b (40 Mbps payload); the paper's mode: 8 Mbps Manchester (16 Mbaud), as transmitted. LT3757 flyback APD bias 150–420 V. USB-C powered; verify on any laptop over USB, no FPGA attached.

Pass 125

2026-11-05 16:52 PST (2026-11-06T00:52:47Z UTC) · commit 3b0f4fd (3b0f4fd52ba21bd2804e7f19e9ce4a93aa138f82)

ADOPTED

COURTYARD CAMPAIGN item 0 (audit blindness): courtyards drawn for the five drawable blind footprints D1, D2, C4, U9, T1 — board instances + hw/pdlvds.pretty library (text insertion of fp_line rectangles: KiCad 7.0.11’s writer zeroes FP_SHAPE points set through the Python API, verified in-session; hw/draw_courtyards.py is the instrument). Blind list 6 -> 1: SH1 remains (shield can enclosing the frontend it covers by design; closure is the pending clip-pattern conversion, parts audit; the audit’s bbox-fallback line reports it every pass). Drawing the courtyards REVEALED 8 new gated pairs, now counted and queued: L1xD2, L2xD2, D2xC36, D2xR35, D2xU11, D2xRJ2, C32xT1, D11xT1. BOARD STATE: courtyard pairs 26 -> 34, nets 24 -> 24, violations 71 -> 71 (courtyard shapes carry no copper; no parts moved, no victims). Next: D2 cluster (move D2, the DNP alternate APD site), T1 pair (move C32, D11), then the original 26.

Nets fully routednot recorded
Pins failednot recorded
Clearance violations71
Unconnected nets24
Audit verdictFAIL

Routes — all copper layers and each layer

F.Cu In1.Cu In2.Cu B.Cu

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