PDLVDS-RX — photodiode LVDS receiver

Clean-room receiver for the Miniscope Zero optical uplink: Excelitas C30737LH Si APD → OPA657 TIA → LMH7220 comparator (LVDS out, DAC-set threshold) → ADN2813 CDR → STM32H723 + USB3300 USB-HS. Design target: 50 Mbps line rate, 8b/10b (40 Mbps payload); the paper's mode: 8 Mbps Manchester (16 Mbaud), as transmitted. LT3757 flyback APD bias 150–420 V. USB-C powered; verify on any laptop over USB, no FPGA attached.

Pass 109

2026-11-05 08:59 PST (2026-11-05T16:59:39Z UTC) · commit d408fc5 (d408fc552430493917d875229dcb91165091bebd)

ADOPTED

HV_RAW re-approach (hw/fix_hvraw.py): heal’s B.Cu surface diagonal ripped (63 items) and the D9.1 haul re-bridged on In2 – F neck to via (5.38,-24.88), In2 southern run y=-24.88 to x=22.2, corridor north at x=22.2, northern approach into via W (34.12,-11.88), F necks into the D5.1 web; D9 pour notch (notch.py species, rule areas 1.25,-27.5..7.03,-22.5 on F+B) added so the pours hold >=1.0 mm from the D9 pocket. Every placed shape was tested against the audit’s own item model including zone fills. DELTAS vs pass 108: nets 33->33 (join retained, mechanism changed), violations 120->87 (-33: -32 HV_RAW diagonal-vs-pour lines removed by the rip, -1 pre-existing ‘HV_RAW D9.1 vs GND zone’ line cured by the notch, +0 new lines from the In2 bridge). Acceptance test PASSED (full audit results/audit-exp82.txt: 33/87; the single exp82-vs-exp79 newcomer, XI vs the CDR_DATP via, belongs to pass 108’s CDR_DATP join).

Nets fully routednot recorded
Pins failednot recorded
Clearance violations87
Unconnected nets33
Audit verdictFAIL

Routes — all copper layers and each layer

F.Cu In1.Cu In2.Cu B.Cu

Top

Pass 109 — top

Bottom

Pass 109 — bottom

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