PDLVDS-RX — photodiode LVDS receiver

Clean-room receiver for the Miniscope Zero optical uplink: Excelitas C30737LH Si APD → OPA657 TIA → LMH7220 comparator (LVDS out, DAC-set threshold) → ADN2813 CDR → STM32H723 + USB3300 USB-HS. Design target: 50 Mbps line rate, 8b/10b (40 Mbps payload); the paper's mode: 8 Mbps Manchester (16 Mbaud), as transmitted. LT3757 flyback APD bias 150–420 V. USB-C powered; verify on any laptop over USB, no FPGA attached.

Pass 159

2026-11-06 06:19 PST (2026-11-06T14:19:35Z UTC) · commit 6f6877c (6f6877cf4bd30d7bbad2495326596a88772a1053)

ADOPTED

pass 159: +VA hop group joined to the main tree - 0.5/0.3 via in C44.1 pad (30.825,40.05), In1 track west at y=40 from the U3.5 hop via (37.725,39.975), passing 0.425 clear of the CMP_IN and THR_FILT vias. DRC: violations 156 -> 156 (class table unchanged), unconnected 50 -> 49, +VA items 4 -> 3 (U13 pair, U1.7, R5.1 remain)

Nets fully routednot recorded
Pins failednot recorded
Clearance violations71
Unconnected nets39
Audit verdictFAIL

Routes — all copper layers and each layer

All layers
All layers — click the image to open the full-size SVG in a new tab.
All layersAll layers F.Cu layerF.CuIn1.Cu layerIn1.CuIn2.Cu layerIn2.CuB.Cu layerB.Cu

F.Cu In1.Cu In2.Cu B.Cu

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