PDLVDS-RX — photodiode LVDS receiver

Clean-room receiver for the Miniscope Zero optical uplink: Excelitas C30737LH Si APD → OPA657 TIA → LMH7220 comparator (LVDS out, DAC-set threshold) → ADN2813 CDR → STM32H723 + USB3300 USB-HS. Design target: 50 Mbps line rate, 8b/10b (40 Mbps payload); the paper's mode: 8 Mbps Manchester (16 Mbaud), as transmitted. LT3757 flyback APD bias 150–420 V. USB-C powered; verify on any laptop over USB, no FPGA attached.

Pass 173

2026-11-06 10:57 PST (2026-11-06T18:57:16Z UTC) · commit d8b6d3f (d8b6d3fb24e6c6986138224fdc4c661981b3336a)

ADOPTED

pass 173: CDR_DATN connected (DATP via relayed west to (66.22,33.28) d0.5 freeing the F thread; DATN F thread (66.5,34.4)->(66.9,32.4), via d0.5, B stepped dive south of DATP staircase around GND/+3V3D/DATP-bottom vias, joining own B channel at (78.375,22.125)). KiCad DRC: unconnected 32->31, violations 156 unchanged (clearance 0, shorting 0, dangling 0)

Nets fully routednot recorded
Pins failednot recorded
Clearance violations101
Unconnected nets27
Audit verdictFAIL

Routes — all copper layers and each layer

All layers
All layers — click the image to open the full-size SVG in a new tab.
All layersAll layers F.Cu layerF.CuIn1.Cu layerIn1.CuIn2.Cu layerIn2.CuB.Cu layerB.Cu

F.Cu In1.Cu In2.Cu B.Cu

Top

Pass 173 — top

Bottom

Pass 173 — bottom

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