PDLVDS-RX — photodiode LVDS receiver

Clean-room receiver for the Miniscope Zero optical uplink: Excelitas C30737LH Si APD → OPA657 TIA → LMH7220 comparator (LVDS out, DAC-set threshold) → ADN2813 CDR → STM32H723 + USB3300 USB-HS. Design target: 50 Mbps line rate, 8b/10b (40 Mbps payload); the paper's mode: 8 Mbps Manchester (16 Mbaud), as transmitted. LT3757 flyback APD bias 150–420 V. USB-C powered; verify on any laptop over USB, no FPGA attached.

Pass 32

2026-11-04 07:33 PST (2026-11-04T15:33:34Z UTC) · commit d3c2952 (d3c2952a8374d83f88feaebb256879385555402c)

ADOPTED

via-first hand stubs (hw/hand_via.py; via disc tested as a zero-length segment after the plus-shape bug was found): +3V3A U9.5 via@(9.27,48) with In2 tail — the last U9 pin; CDR_LOS U4.22 second escape via@(55.29,51.25)

Nets fully routednot recorded
Pins failednot recorded
Clearance violations36
Unconnected nets55
Audit verdictFAIL

Routes — all copper layers and each layer

F.Cu
F.Cu — click the image to open the full-size SVG in a new tab.
F.Cu layerF.CuIn1.Cu layerIn1.CuIn2.Cu layerIn2.CuB.Cu layerB.Cu

F.Cu In1.Cu In2.Cu B.Cu

Top

Pass 32 — top

Bottom

Pass 32 — bottom

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