PDLVDS-RX — photodiode LVDS receiver

Clean-room receiver for the Miniscope Zero optical uplink: Excelitas C30737LH Si APD → OPA657 TIA → LMH7220 comparator (LVDS out, DAC-set threshold) → ADN2813 CDR → STM32H723 + USB3300 USB-HS. Design target: 50 Mbps line rate, 8b/10b (40 Mbps payload); the paper's mode: 8 Mbps Manchester (16 Mbaud), as transmitted. LT3757 flyback APD bias 150–420 V. USB-C powered; verify on any laptop over USB, no FPGA attached.

Pass 172

2026-11-06 08:56 PST (2026-11-06T16:56:56Z UTC) · commit 9448211 (9448211f01c6f570afa9d81c34cf33321fefc0a9)

ADOPTED

pass 172: HV_GATE connected (grid B path R27.1 to U10 district, F w0.15 needle thread between U10.6 pad corner and HV_SHDN via to via (31.6,-1.55), B stub to path end). DRC: unconnected 33->32, violations 156 unchanged (clearance 0, shorting 0)

Nets fully routednot recorded
Pins failednot recorded
Clearance violations101
Unconnected nets28
Audit verdictFAIL

Routes — all copper layers and each layer

All layers
All layers — click the image to open the full-size SVG in a new tab.
All layersAll layers F.Cu layerF.CuIn1.Cu layerIn1.CuIn2.Cu layerIn2.CuB.Cu layerB.Cu

F.Cu In1.Cu In2.Cu B.Cu

Top

Pass 172 — top

Bottom

Pass 172 — bottom

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