PDLVDS-RX — photodiode LVDS receiver

Clean-room receiver for the Miniscope Zero optical uplink: Excelitas C30737LH Si APD → OPA657 TIA → LMH7220 comparator (LVDS out, DAC-set threshold) → ADN2813 CDR → STM32H723 + USB3300 USB-HS. Design target: 50 Mbps line rate, 8b/10b (40 Mbps payload); the paper's mode: 8 Mbps Manchester (16 Mbaud), as transmitted. LT3757 flyback APD bias 150–420 V. USB-C powered; verify on any laptop over USB, no FPGA attached.

Pass 73

2026-11-04 18:32 PST (2026-11-05T02:32:56Z UTC) · commit d8347be (d8347becf263210813b188cbc5920c353301fa50)

ADOPTED

hand_via campaign on the 16 no-stub pads from the pass-70 record (exp8 -> exp9): only 1/16 placed (ULPI_STP U6.26, via@(64.83,36.96) + In2 tail). The other 15 are proven outside hand_via’s straight-neck/single-via shape space on exp8 geometry, each by 1-3 blockers (probe: results/probe-via.txt): U9.5 neck blocked solely by GND pad U9.7; U10.7 via disc solely by one +5V track; D1.5 by APD_A pads D1.4/D1.6 at the 1.0 mm HV class (intrinsic package geometry); J1.B5 by VBUS_RAW in the connector field; U6.74 by the NRST track bundle across the pin tips. These pads go to the residue loop’s rip-up healing, which can move the blockers.

Nets fully routednot recorded
Pins failednot recorded
Clearance violations40
Unconnected nets33
Audit verdictFAIL

Routes — all copper layers and each layer

F.Cu In1.Cu In2.Cu B.Cu

Top

Pass 73 — top

Bottom

Pass 73 — bottom

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