PDLVDS-RX — photodiode LVDS receiver

Clean-room receiver for the Miniscope Zero optical uplink: Excelitas C30737LH Si APD → OPA657 TIA → LMH7220 comparator (LVDS out, DAC-set threshold) → ADN2813 CDR → STM32H723 + USB3300 USB-HS. Design target: 50 Mbps line rate, 8b/10b (40 Mbps payload); the paper's mode: 8 Mbps Manchester (16 Mbaud), as transmitted. LT3757 flyback APD bias 150–420 V. USB-C powered; verify on any laptop over USB, no FPGA attached.

Pass 119

2026-11-05 14:32 PST (2026-11-05T22:32:25Z UTC) · commit 7ddc20b (7ddc20bdc9cde5ecf3a6e41300897ea028327b80)

ADOPTED

CC2 rejoined (queue item 3): F hop (30.50,72.55)->(31.30,72.34)->(31.90,72.30) w=0.20 threaded through the 0.125 mm window at x=31.10 between J1.B4’s pad (0.25 class) and J1.A9’s escape start. VBUS_RAW’s F jumper (31.15,72.83)->(31.00,71.98) – A9’s sole link – ripped and repaid in the same pass: escape extended (31.85,70.88)->(32.05,70.68), via (32.05,70.68), B run south then diagonal west onto VBUS_RAW’s own B diagonal chain at (28.00,72.25); VBUS_RAW still 1 group. First hop cut cost +3 (74->77: B4 pad + A9 escape x2) and was re-approached, not kept. DELTAS vs pass 118: nets 29->28 (CC2 connected), violations 74->74, census byte-identical. No victims (VBUS_RAW repaid in-pass).

Nets fully routednot recorded
Pins failednot recorded
Clearance violations74
Unconnected nets28
Audit verdictFAIL

Routes — all copper layers and each layer

All layers
All layers — click the image to open the full-size SVG in a new tab.
All layersAll layers F.Cu layerF.CuIn1.Cu layerIn1.CuIn2.Cu layerIn2.CuB.Cu layerB.Cu

F.Cu In1.Cu In2.Cu B.Cu

Top

Pass 119 — top

Bottom

Pass 119 — bottom

← Pass 118 · all passes · Pass 120 →