PDLVDS-RX — photodiode LVDS receiver

Clean-room receiver for the Miniscope Zero optical uplink: Excelitas C30737LH Si APD → OPA657 TIA → LMH7220 comparator (LVDS out, DAC-set threshold) → ADN2813 CDR → STM32H723 + USB3300 USB-HS. Design target: 50 Mbps line rate, 8b/10b (40 Mbps payload); the paper's mode: 8 Mbps Manchester (16 Mbaud), as transmitted. LT3757 flyback APD bias 150–420 V. USB-C powered; verify on any laptop over USB, no FPGA attached.

Pass 160

2026-11-06 06:22 PST (2026-11-06T14:22:59Z UTC) · commit 3dab785 (3dab7852c4e6d0817fb3b8b6755a58cd1b13b34a)

ADOPTED

pass 160: +VA U1.7 joined to the tree - 0.5/0.3 vias in U1.7 pad (18.5,39.365) and U2.5 pad (25.95,39.05), straight In1 track between (In1/In2 carry no tracks in the front-end district). DRC: violations 156 -> 156 (class table unchanged), unconnected 49 -> 48, +VA items 3 -> 2 (U13 pair and R5.1 remain)

Nets fully routednot recorded
Pins failednot recorded
Clearance violations71
Unconnected nets39
Audit verdictFAIL

Routes — all copper layers and each layer

All layers
All layers — click the image to open the full-size SVG in a new tab.
All layersAll layers F.Cu layerF.CuIn1.Cu layerIn1.CuIn2.Cu layerIn2.CuB.Cu layerB.Cu

F.Cu In1.Cu In2.Cu B.Cu

Top

Pass 160 — top

Bottom

Pass 160 — bottom

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