PDLVDS-RX — photodiode LVDS receiver

Clean-room receiver for the Miniscope Zero optical uplink: Excelitas C30737LH Si APD → OPA657 TIA → LMH7220 comparator (LVDS out, DAC-set threshold) → ADN2813 CDR → STM32H723 + USB3300 USB-HS. Design target: 50 Mbps line rate, 8b/10b (40 Mbps payload); the paper's mode: 8 Mbps Manchester (16 Mbaud), as transmitted. LT3757 flyback APD bias 150–420 V. USB-C powered; verify on any laptop over USB, no FPGA attached.

Pass 168

2026-11-06 07:36 PST (2026-11-06T15:36:13Z UTC) · commit d53221c (d53221c743ca76e66b6a8ccd8b05b868c4995d68)

ADOPTED

pass 168: CF1 connected (violations 156 -> 156, unconnected 40 -> 39). Pure-F route U4.15 -> C15.1: north leg at x=67.55 (w0.15 past the CF2 jog), bent east run at y=40.52 clearing U4.16’s pad top, north at x=68.6, west over the C15 pads at y=42.05, south into C15.1. Also recorded as parked/sealed this session: HV_GATE, HV_INTVCC, USB_RST, XI, XO, PHY_1V8A, CDR_NIN, REFCLKN, +3V3A U7.6 (each with named blockers in the pass-167/168 working notes).

Nets fully routednot recorded
Pins failednot recorded
Clearance violations93
Unconnected nets34
Audit verdictFAIL

Routes — all copper layers and each layer

All layers
All layers — click the image to open the full-size SVG in a new tab.
All layersAll layers F.Cu layerF.CuIn1.Cu layerIn1.CuIn2.Cu layerIn2.CuB.Cu layerB.Cu

F.Cu In1.Cu In2.Cu B.Cu

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Pass 168 — top

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Pass 168 — bottom

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