PDLVDS-RX — photodiode LVDS receiver

Clean-room receiver for the Miniscope Zero optical uplink: Excelitas C30737LH Si APD → OPA657 TIA → LMH7220 comparator (LVDS out, DAC-set threshold) → ADN2813 CDR → STM32H723 + USB3300 USB-HS. Design target: 50 Mbps line rate, 8b/10b (40 Mbps payload); the paper's mode: 8 Mbps Manchester (16 Mbaud), as transmitted. LT3757 flyback APD bias 150–420 V. USB-C powered; verify on any laptop over USB, no FPGA attached.

Pass 27

2026-11-04 07:06 PST (2026-11-04T15:06:52Z UTC) · commit 8b6204d (8b6204dfcbe60967165e9a2e6a93e0287ae7a9d1)

ADOPTED

U9 cluster clearing (disc 8,48 r3.4): 0/4 — full clearing changed nothing; U9’s pins are sealed by their own exposed pad (0.075 mm) inside the router’s centre-anchored fanout model; hand-placed stubs are the route (the audit judges exact shapes, the model anchors at pad centres)

Nets fully routednot recorded
Pins failednot recorded
Clearance violations13
Unconnected nets50
Audit verdictFAIL

Routes — all copper layers and each layer

F.Cu
F.Cu — click the image to open the full-size SVG in a new tab.
F.Cu layerF.CuIn1.Cu layerIn1.CuIn2.Cu layerIn2.CuB.Cu layerB.Cu

F.Cu In1.Cu In2.Cu B.Cu

Top

Pass 27 — top

Bottom

Pass 27 — bottom

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