PDLVDS-RX — photodiode LVDS receiver

Clean-room receiver for the Miniscope Zero optical uplink: Excelitas C30737LH Si APD → OPA657 TIA → LMH7220 comparator (LVDS out, DAC-set threshold) → ADN2813 CDR → STM32H723 + USB3300 USB-HS. Design target: 50 Mbps line rate, 8b/10b (40 Mbps payload); the paper's mode: 8 Mbps Manchester (16 Mbaud), as transmitted. LT3757 flyback APD bias 150–420 V. USB-C powered; verify on any laptop over USB, no FPGA attached.

Pass 180

2026-11-06 15:19 PST (2026-11-06T23:19:21Z UTC) · commit f6c425c (f6c425c4abfd99a7e0e61718ab0a29721d3156a3)

ADOPTED

pass 180: CDR_NIN connected — C13’s move (pass 179) vacated U4.4’s row; F stub west to via (61.75,36.7) (the (62.8,37.05) dive dies on B against CDR_VREF’s staircase vertical), In2 north of the DM_PHY northern staircase, around the +3V3D_CDR staircase west end (rounding shifted west in t_y2 to clear the d0.8 staircase via by 0.44), then SW on the open south-west side of DM_PHY’s long In2 staircase to via (51.45,45.5) and F tail into C9.2. DRC: unconnected 23->22, violations 154->154 (identical class table), clearance/shorting/dangling 0

Nets fully routednot recorded
Pins failednot recorded
Clearance violations108
Unconnected nets19
Audit verdictFAIL

Routes — all copper layers and each layer

All layers
All layers — click the image to open the full-size SVG in a new tab.
All layersAll layers F.Cu layerF.CuIn1.Cu layerIn1.CuIn2.Cu layerIn2.CuB.Cu layerB.Cu

F.Cu In1.Cu In2.Cu B.Cu

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Pass 180 — top

Bottom

Pass 180 — bottom

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