PDLVDS-RX — photodiode LVDS receiver

Clean-room receiver for the Miniscope Zero optical uplink: Excelitas C30737LH Si APD → OPA657 TIA → LMH7220 comparator (LVDS out, DAC-set threshold) → ADN2813 CDR → STM32H723 + USB3300 USB-HS. Design target: 50 Mbps line rate, 8b/10b (40 Mbps payload); the paper's mode: 8 Mbps Manchester (16 Mbaud), as transmitted. LT3757 flyback APD bias 150–420 V. USB-C powered; verify on any laptop over USB, no FPGA attached.

Pass 127

2026-11-05 17:14 PST (2026-11-06T01:14:00Z UTC) · commit 1a5ecb6 (1a5ecb63172159b0824785c7cda42821b5b75325)

ADOPTED

COURTYARD CAMPAIGN item 2 (D2 + T1 clusters): D2 (18,60)->(28,60) closing all six pairs its newly drawn courtyard revealed (L1, L2, C36, R35, U11, RJ2); C32 (40.5,-17)->(40.5,-16.4) and D11 (21,-25)->(17,-29.5) closing C32xT1 and D11xT1 (D11 boxed by D9/D10 west, T1 east/south, Q1 north; nearest pocket SW, 10 segments re-laid clean). APD_K_ALT held by relay; C32 and D11 nets unchanged. VICTIM NAMED AS OWED: APD_A_ALT D2 leg (1->2 groups) – repays in the resumed routing queue. prune_dead run after the moves. Remaining courtyard pairs: 19, of which U6xMH2 is the neither-may-move case escalated to the parent.

Nets fully routednot recorded
Pins failednot recorded
Clearance violations118
Unconnected nets31
Audit verdictFAIL

Routes — all copper layers and each layer

All layers
All layers — click the image to open the full-size SVG in a new tab.
All layersAll layers F.Cu layerF.CuIn1.Cu layerIn1.CuIn2.Cu layerIn2.CuB.Cu layerB.Cu

F.Cu In1.Cu In2.Cu B.Cu

Top

Pass 127 — top

Bottom

Pass 127 — bottom

← Pass 126 · all passes · Pass 128 →