PDLVDS-RX — photodiode LVDS receiver

Clean-room receiver for the Miniscope Zero optical uplink: Excelitas C30737LH Si APD → OPA657 TIA → LMH7220 comparator (LVDS out, DAC-set threshold) → ADN2813 CDR → STM32H723 + USB3300 USB-HS. Design target: 50 Mbps line rate, 8b/10b (40 Mbps payload); the paper's mode: 8 Mbps Manchester (16 Mbaud), as transmitted. LT3757 flyback APD bias 150–420 V. USB-C powered; verify on any laptop over USB, no FPGA attached.

Pass 59

2026-11-04 12:16 PST (2026-11-04T20:16:51Z UTC) · commit 7ea91c7 (7ea91c721a3bdc0afca185513cd7c7b167e6ae3c)

ADOPTED

D1.6 link segment from the pad’s NW corner to its fanout chain: APD_A fully connected (36 unconnected nets). The segment passes D1.5 at ~0.96 mm — the 4th item of the justified D1 package-geometry graze family (the APD’s own terminals are 0.5 mm apart; the 1.0 mm board rule cannot be met inside the footprint)

Nets fully routednot recorded
Pins failednot recorded
Clearance violations4
Unconnected nets36
Audit verdictFAIL

Routes — all copper layers and each layer

F.Cu
F.Cu — click the image to open the full-size SVG in a new tab.
F.Cu layerF.CuIn1.Cu layerIn1.CuIn2.Cu layerIn2.CuB.Cu layerB.Cu

F.Cu In1.Cu In2.Cu B.Cu

Top

Pass 59 — top

Bottom

Pass 59 — bottom

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