PDLVDS-RX — photodiode LVDS receiver

Clean-room receiver for the Miniscope Zero optical uplink: Excelitas C30737LH Si APD → OPA657 TIA → LMH7220 comparator (LVDS out, DAC-set threshold) → ADN2813 CDR → STM32H723 + USB3300 USB-HS. Design target: 50 Mbps line rate, 8b/10b (40 Mbps payload); the paper's mode: 8 Mbps Manchester (16 Mbaud), as transmitted. LT3757 flyback APD bias 150–420 V. USB-C powered; verify on any laptop over USB, no FPGA attached.

Pass 80

2026-11-04 22:46 PST (2026-11-05T06:46:17Z UTC) · commit addb328 (addb328862b3e3ab29a944e1d8fe52b3ea4e6161)

ADOPTED

U10.9 HV_SHDN connected (Class A): step-1 dense retest at the true 0.20 class found the one clear via site (17.25,-15.45) the radial probes never sampled — escape placed (hw/surgery_u10_9_escape.py: neck w=0.20, via 0.6/0.3, In2 tail east). heal_nets and thread_far both refused the pair (gap 6.28); the tail was hand-extended on In2 around the cluster (segments probe-verified with hw/probe_path.py) via (20.5,-21) west to the divider web, via up at (9.5,-18.9), F neck into the main track (hw/surgery_u10_9_connect.py), then zones refilled (hw/refill.py) so the pour carves the landing via’s antipad. Audit (corrected checker, tools commit ed0d9b6): nets 30 -> 29; violations 11 = 2 D1 standing + 9 TP_HV (class opened by the census correction, fix queued in the re-sync). HV_SHDN leaves Class A; U10.8/U10.3 seals survive correct classes and ride the re-sync. (Record note: this pass was first committed against commit_pass.py’s default board — the pre-expansion hw/pdlvds_rx.kicad_pcb — and redone in place before any push; always pass –board.)

Nets fully routednot recorded
Pins failednot recorded
Clearance violations11
Unconnected nets29
Audit verdictFAIL

Routes — all copper layers and each layer

F.Cu In1.Cu In2.Cu B.Cu

Top

Pass 80 — top

Bottom

Pass 80 — bottom

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