PDLVDS-RX — photodiode LVDS receiver

Clean-room receiver for the Miniscope Zero optical uplink: Excelitas C30737LH Si APD → OPA657 TIA → LMH7220 comparator (LVDS out, DAC-set threshold) → ADN2813 CDR → STM32H723 + USB3300 USB-HS. Design target: 50 Mbps line rate, 8b/10b (40 Mbps payload); the paper's mode: 8 Mbps Manchester (16 Mbaud), as transmitted. LT3757 flyback APD bias 150–420 V. USB-C powered; verify on any laptop over USB, no FPGA attached.

Pass 167

2026-11-06 07:24 PST (2026-11-06T15:24:58Z UTC) · commit 49f3cc6 (49f3cc6e3299ef142249348cd1f2f4ca9adfb3d5)

ADOPTED

pass 167: HV_VC + HV_VC2 connected (violations 156 -> 156, unconnected 42 -> 40). HV_VC: pure-F route R23.1 -> U10.1 threading south of the HV_FBX F chain. HV_VC2: via-in-pad at C29.1 and R23.2 with a B run passing south of the HV_R29M B staircase (the F corridor between C29.2 and R23.1 pads is 0.05 mm too narrow for a track). HV_GATE and HV_INTVCC investigated and parked as sealed: GATE’s channel between U10 EP and the east pad row fits one 0.15 track but every approach (NE diag, south run, B under the HV_SENSE staircase, In2) is blocked by named copper; INTVCC is sealed on F (SHDN via + U10.9 corner pinch), In2 (HV_FBX staircase) and B (HV_SENSE weave).

Nets fully routednot recorded
Pins failednot recorded
Clearance violations93
Unconnected nets35
Audit verdictFAIL

Routes — all copper layers and each layer

All layers
All layers — click the image to open the full-size SVG in a new tab.
All layersAll layers F.Cu layerF.CuIn1.Cu layerIn1.CuIn2.Cu layerIn2.CuB.Cu layerB.Cu

F.Cu In1.Cu In2.Cu B.Cu

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