PDLVDS-RX — photodiode LVDS receiver

Clean-room receiver for the Miniscope Zero optical uplink: Excelitas C30737LH Si APD → OPA657 TIA → LMH7220 comparator (LVDS out, DAC-set threshold) → ADN2813 CDR → STM32H723 + USB3300 USB-HS. Design target: 50 Mbps line rate, 8b/10b (40 Mbps payload); the paper's mode: 8 Mbps Manchester (16 Mbaud), as transmitted. LT3757 flyback APD bias 150–420 V. USB-C powered; verify on any laptop over USB, no FPGA attached.

Pass 166

2026-11-06 07:00 PST (2026-11-06T15:00:01Z UTC) · commit 5774eff (5774effedc2c85475e6cc96dc8f3a66b36e3a6bb)

ADOPTED

pass 166: TIA_OUT COMPLETE - R7.1 joined: 0.5/0.3 via in R7.1 pad (28.1,39.25), In1 track west at y=39.9 (0.45 clear of the +VA via) to the C5.1 hop track vertex (20.3,39.9). DRC: violations 156 -> 156 (class table unchanged), unconnected 43 -> 42, TIA_OUT items 1 -> 0

Nets fully routednot recorded
Pins failednot recorded
Clearance violations71
Unconnected nets37
Audit verdictFAIL

Routes — all copper layers and each layer

All layers
All layers — click the image to open the full-size SVG in a new tab.
All layersAll layers F.Cu layerF.CuIn1.Cu layerIn1.CuIn2.Cu layerIn2.CuB.Cu layerB.Cu

F.Cu In1.Cu In2.Cu B.Cu

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