PDLVDS-RX — photodiode LVDS receiver

Clean-room receiver for the Miniscope Zero optical uplink: Excelitas C30737LH Si APD → OPA657 TIA → LMH7220 comparator (LVDS out, DAC-set threshold) → ADN2813 CDR → STM32H723 + USB3300 USB-HS. Design target: 50 Mbps line rate, 8b/10b (40 Mbps payload); the paper's mode: 8 Mbps Manchester (16 Mbaud), as transmitted. LT3757 flyback APD bias 150–420 V. USB-C powered; verify on any laptop over USB, no FPGA attached.

Pass 33

2026-11-04 08:00 PST (2026-11-04T16:00:43Z UTC) · commit 128862d (128862d766c8434e7b1abff75698481437a9e54b)

ADOPTED

placement fixes found by exhaustive audit-exact search (hw/place_search.py): C40 to a clean home at (41.5,62) still flipped on the bottom side (its (35,62) B pads grazed PHY_1V8/ULPI_D2 B-tracks — 21 items), R27 west to (18.1,6.0) (its pad 2 grazed +5V tracks — 2 items); APD_A’s D1.6 escape chain ripped (10 items) to open D1.5’s exit

Nets fully routednot recorded
Pins failednot recorded
Clearance violations13
Unconnected nets40
Audit verdictFAIL

Routes — all copper layers and each layer

F.Cu
F.Cu — click the image to open the full-size SVG in a new tab.
F.Cu layerF.CuIn1.Cu layerIn1.CuIn2.Cu layerIn2.CuB.Cu layerB.Cu

F.Cu In1.Cu In2.Cu B.Cu

Top

Pass 33 — top

Bottom

Pass 33 — bottom

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