PDLVDS-RX — photodiode LVDS receiver

Clean-room receiver for the Miniscope Zero optical uplink: Excelitas C30737LH Si APD → OPA657 TIA → LMH7220 comparator (LVDS out, DAC-set threshold) → ADN2813 CDR → STM32H723 + USB3300 USB-HS. Design target: 50 Mbps line rate, 8b/10b (40 Mbps payload); the paper's mode: 8 Mbps Manchester (16 Mbaud), as transmitted. LT3757 flyback APD bias 150–420 V. USB-C powered; verify on any laptop over USB, no FPGA attached.

Pass 178

2026-11-06 13:03 PST (2026-11-06T21:03:35Z UTC) · commit 608a0dc (608a0dce63daa04841d796806b867e7c56e6dc99)

ADOPTED

pass 178: ULPI_D3 connected — D4 via moved west on its own In2 diagonal to (87.35,7.15) (old via at (88.375,6.125) sealed pad69’s fan together with the NC pad row), D4 tail re-laid north (87.35,7.15)->(88.6,6.6)->(89.65,6.45)->(89.78,5.662); D3 In2 rerouted south of D4’s diagonal to via (88.15,5.9), F tail (88.5,6.05)->(89.25,6.05)->dive into U6.69; VCAP2 web re-fanned east ((89.225,7.0)->(89.9,6.9)->(90.25,6.162)) to clear the fan; GND stitch via (88.3,8.6) re-ties the C18.2 F-fill island severed by the fan tracks. DRC: unconnected 26->25, violations 156->156 (identical class table); clearance/shorting/dangling 0

Nets fully routednot recorded
Pins failednot recorded
Clearance violations108
Unconnected nets22
Audit verdictFAIL

Routes — all copper layers and each layer

All layers
All layers — click the image to open the full-size SVG in a new tab.
All layersAll layers F.Cu layerF.CuIn1.Cu layerIn1.CuIn2.Cu layerIn2.CuB.Cu layerB.Cu

F.Cu In1.Cu In2.Cu B.Cu

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Pass 178 — top

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Pass 178 — bottom

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