PDLVDS-RX — photodiode LVDS receiver

Clean-room receiver for the Miniscope Zero optical uplink: Excelitas C30737LH Si APD → OPA657 TIA → LMH7220 comparator (LVDS out, DAC-set threshold) → ADN2813 CDR → STM32H723 + USB3300 USB-HS. Design target: 50 Mbps line rate, 8b/10b (40 Mbps payload); the paper's mode: 8 Mbps Manchester (16 Mbaud), as transmitted. LT3757 flyback APD bias 150–420 V. USB-C powered; verify on any laptop over USB, no FPGA attached.

Pass 78

2026-11-04 21:55 PST (2026-11-05T05:55:12Z UTC) · commit 6b8c0bc (6b8c0bc27e008c52c006b047df6f885ddb3fcce9)

ADOPTED

U10 locality surgery 1 (Class A): U10.7 via escape placed in its proven east window — F neck (16.79,-14.50)->(17.20,-14.50), via 0.6/0.3 @(17.20,-14.50), In2 tail ->(19.20,-14.50), every shape collision-tested pre-placement (results/surgery-u10-escape.txt). Audit: violations still 2 (D1 standing lines only), nets 31 — HV_GATE’s U10.7 group now reaches open field on In2. The companion +5V-trunk jog FAILED and is recorded: a MOS_G track fences every jog depth 18.95-20.10 (results/surgery-u10-jog.txt); U10.8/U10.9/U10.3 remain sealed by row arithmetic (0.5 pitch, 0.30 pads, 0.25 HV class: channel 0.70 < 0.75 demanded) plus that palisade.

Nets fully routednot recorded
Pins failednot recorded
Clearance violations2
Unconnected nets31
Audit verdictFAIL

Routes — all copper layers and each layer

All layers
All layers — click the image to open the full-size SVG in a new tab.
All layersAll layers F.Cu layerF.CuIn1.Cu layerIn1.CuIn2.Cu layerIn2.CuB.Cu layerB.Cu

F.Cu In1.Cu In2.Cu B.Cu

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