PDLVDS-RX — photodiode LVDS receiver

Clean-room receiver for the Miniscope Zero optical uplink: Excelitas C30737LH Si APD → OPA657 TIA → LMH7220 comparator (LVDS out, DAC-set threshold) → ADN2813 CDR → STM32H723 + USB3300 USB-HS. Design target: 50 Mbps line rate, 8b/10b (40 Mbps payload); the paper's mode: 8 Mbps Manchester (16 Mbaud), as transmitted. LT3757 flyback APD bias 150–420 V. USB-C powered; verify on any laptop over USB, no FPGA attached.

Pass 93

2026-11-05 04:03 PST (2026-11-05T12:03:31Z UTC) · commit 677fc3e (677fc3e65174b22f39ee6f07f6c11246e247f26e)

ADOPTED

Escapes 10 (exp50 -> exp51): CC2 COMPLETE (east jog at y=72.3 under the A9/B4 pads) + VBUS_RAW re-feed placed; HV pocket sections refused on named blockers (R31.2 shadow, APD_K via, ILIM_A B track) – batch 11 re-plans them with real pad bboxes. Audit records the state.

Nets fully routednot recorded
Pins failednot recorded
Clearance violations82
Unconnected nets28
Audit verdictFAIL

Routes — all copper layers and each layer

All layers
All layers — click the image to open the full-size SVG in a new tab.
All layersAll layers F.Cu layerF.CuIn1.Cu layerIn1.CuIn2.Cu layerIn2.CuB.Cu layerB.Cu

F.Cu In1.Cu In2.Cu B.Cu

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